Volume 4, Issue 1, June 2020, Page: 10-15
Inverted Gate Vedic Multiplier in 90nm CMOS Technology
Chiranjit Rajendra Patel, Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Vivek Bettadapura Adishesha, Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Vivek Urankar, Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Keshav Vaidyanathan Bharadwaj, Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Received: Jun. 16, 2020;       Accepted: Jun. 30, 2020;       Published: Jul. 7, 2020
DOI: 10.11648/j.ajece.20200401.12      View  60      Downloads  57
Abstract
This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.
Keywords
CMOS 90nm, Inverted Gate, Vedic Multiplier, Urdhva Tiryagbhayam, Carry Save Adder, Layout Design
To cite this article
Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj, Inverted Gate Vedic Multiplier in 90nm CMOS Technology, American Journal of Electrical and Computer Engineering. Vol. 4, No. 1, 2020, pp. 10-15. doi: 10.11648/j.ajece.20200401.12
Copyright
Copyright © 2020 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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