Volume 3, Issue 1, June 2019, Page: 38-45
An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]
Mahesh Kumar, Department of Electronics, PSG College of Arts & Science, Coimbatore, India
Received: Nov. 29, 2018;       Accepted: Jan. 5, 2019;       Published: Jul. 2, 2019
DOI: 10.11648/j.ajece.20190301.15      View  603      Downloads  164
In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.
Fault Diagnosis, Built-in Self-Test (BIST), Configurable Logic Block (CLB), Field-Programmable Gate Array (FPGA), Testing
To cite this article
Mahesh Kumar, An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST], American Journal of Electrical and Computer Engineering. Vol. 3, No. 1, 2019, pp. 38-45. doi: 10.11648/j.ajece.20190301.15
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